The Tez soft IP core is written using Verilog and System Verilog HDL language. The soft IP core can be used ASIC/VLSI development purposes. Most tiles contain processing, memory, and communication routers. Processing in a tile is done with CPU cores and specialized accelerator cores. The accelerator cores are added to personalize the Tez architecture and to improve energy/performance for targeted applications.
Product Overview
The Tez soft IP core consists of 32 POSIT cores. Best suited for automotive applications, compatible for all floating-point instructions, supported with VividSparks POSIT compiler.
VividSparks products are based on number system called POSIT. POSIT number system is alternative to IEEE-754 FP number system with better dynamic range, accuracy, less exceptions, no overflow and no under flow. POSIT number system require half data width with respect to IEEE-754 FP. For example, POSIT require 16 bits to compute 32 bits accuracy of equivalent IEEE-754 single precision FP, POSIT require 32 bits to compute 64 bits accuracy of equivalent IEEE-754 double precision, etc. VividSparks products are quite powerful in AI, ML, HPC, edge computing, and graphics computing applications keeping low memory requirements and high performance.
Version 1.1.0
By VividSparks IT Solutions Pvt. Ltd.
Catagories Automotive
Technology Used Technology independent IP core
Delivery Method Verilog/System Verilog source codes
Contact info@vividsparks.tech
Highlights
- Highly optimized and fully pipelined architecture
- Ready to integrate with any 3rd party IP cores
Usage Instructions
Please contact us for instructions.
Support Information
VividSparks Support offers four support plans: Basic, Developer, Business, and Enterprise. The Basic plan is free of charge and offers support for account and billing questions. The other plans offer an unlimited number of technical support cases with pay-by-the-month pricing and providing the level of support that meets your needs.