The Tez FPGA (field programmable gate array) Image built using Xilinx Alveo U200 board with CentOS 7. The FGPA image is pre-built with Xilinx FPGA development tools and run time tools required to develop and use custom FPGAs for hardware acceleration.
Product Overview
The Tez FPGA image consists of 32 POSIT cores. Best suited for automotive applications, compatible for all floating-point instructions, supported with VividSparks POSIT compiler.
VividSparks products are based on number system called POSIT. POSIT number system is alternative to IEEE-754 FP number system with better dynamic range, accuracy, less exceptions, no overflow and no under flow. POSIT number system require half data width with respect to IEEE-754 FP. For example, POSIT require 16 bits to compute 32 bits accuracy of equivalent IEEE-754 single precision FP, POSIT require 32 bits to compute 64 bits accuracy of equivalent IEEE-754 double precision, etc. VividSparks products are quite powerful in AI, ML, HPC, edge computing, and graphics computing applications keeping low memory requirements and high performance.
Version 1.2.0
By VividSparks IT Solutions Pvt. Ltd.
Catagories Automotive
Operating System CentOS 7.0
Delivery Method VividSparks Machine Image
Contact info@vividsparks.tech
Highlights
- Developed using Alveo U200 with Vivado 2019.1
- U200 Integration - includes packages and configurations
Usage Instructions
Please
Support Information
VividSparks Support offers four support plans: Basic, Developer, Business, and Enterprise. The Basic plan is free of charge and offers support for account and billing questions. The other plans offer an unlimited number of technical support cases with pay-by-the-month pricing and providing the level of support that meets your needs.