The RacEr GPGPU FPGA (field programmable gate array) Image built using Xilinx Alveo U200 board with CentOS 7. The FGPA image is pre-built with Xilinx FPGA development tools and run time tools required to develop and use custom FPGAs for hardware acceleration.
The RacEr FPGA image consists of array of processing elements. Premium GPU architecture configurable up to 512 cores. More POSIT operations per watt, supports ploating point (FP) equivalent POSIT instructions, supports CUDA equivalent programming model.
VividSparks products are based on number system called POSIT. POSIT number system is alternative to IEEE-754 FP number system with better dynamic range, accuracy, less exceptions, no overflow and no under flow. POSIT number system require half data width with respect to IEEE-754 FP. For example, POSIT require 16 bits to compute 32 bits accuracy of equivalent IEEE-754 single precision FP, POSIT require 32 bits to compute 64 bits accuracy of equivalent IEEE-754 double precision, etc. VividSparks products are quite powerful in AI, ML, HPC, edge computing, and graphics computing applications keeping low memory requirements and high performance.
Version 1.2.0
By VividSparks IT Solutions Pvt. Ltd.
Catagories GPU acceleration
Operating System CentOS 7.0
Delivery Method VividSparks Machine Image
Contact info@vividsparks.tech